1. Field of the Invention
This invention relates to digital data communication between stations connected in a series loop configuration which does not require a master control unit and carries out memory-to-memory communication between processors attached to the loop stations.
2. Description of the Prior Art
Present multi-processor systems perform communication between processors in a channel mode wherein dedicated lines and connections are arranged between the processors through an I/O control unit. This requires extensive lines for interlock control and data transmission between any two processors. U.S. pat. Nos. 4,014,005 and 3,916,380 describe typical systems which carry out this dedicated channel mode of communication between processors.
In certain applications advantages over the dedicated channel mode have been found in the loop configuration with a common buss connecting the attached units. This gives flexibility in permitting a processor to be attached to the loop for carrying on communication with any other processor attached to the loop.
The present loop communication systems between processors use a master controller attached to the loop for directing communication between all attached processors. The control functions are carried out by using separate control lines on the loop, polling techniques between processors on the loop for direction of transmission and extensive interlock protocol. U.S. Pat. Nos. 3,639,904; 3,659,271; 3,876,838; 3,879,710; 3,883,693; 4,002,842 are typical of the loop system with a separate control unit.
Other loop communication systems use a fixed time frame format for synchronization between attached processors. This technique allots a specific time frame for each processor on the loop to transmit or receive data during the time frame or frames assigned to that processor. This type system is limited in speed and capacity by (i) the allotment of time frames to processors which have no data at that particular time to communicate, and (ii) the interlocking of the master unit which generates the frames. U.S. Pat. Nos. 3,483,329; 3,544,976; and 3,755,789 each disclose a fixed time frame communication system.
To summarize, the prior art systems for communication between processors are of the dedicated channel type which require extensive lines and interlock control; the loop communications system with the added complexity of a master control unit attached to the loop; or the loop-type system with the assigned time frame mode of communication having the limitations of low capacity and slow communication time.